Various television cameras using a solid state image pickup device as an device have been proposed, and television cameras using a charge-coupled device (CCD) as a solid sate image pickup device have been widely used. In a CCD camera, a signal read out of the CCD is sampled by a sampling circuit, for example a correlative double sampling circuit, is passed through analog signal processing circuits which perform a filtering process to remove clock noise, a gain control, a non-linear processing, and the like, and then is sampled and converted into a digital image signal by means of an analog-to-digital converter to take out a television image signal. The analog-to-digital converter samples and holds a digital image signal by means of a sample and hold circuit and converts the thus held signal to a digital signal. In the case where a flash type analog-to-digital converter is used and as the analog-to-digital converter, an input analog image signal is directly converted into a digital image signal, and the analog-to-digital conversion is performed in synchronism with the sampling pulse. In order to distinguish the sampling pulse used in the analog-to-digital converter from the sampling pulse used in the correlative double sampling circuit, in this specification the former sampling pulse is called a sampling pulse for analog-to-digital conversion.
A known solid state image pickup apparatus whose block diagram is shown in FIG. 1 reads a CCD 1 with a driving pulse from a CCD driving gate array 3 for generating a CCD driving signal in response to a reference clock signal generated by a reference oscillator (OSC) 2, samples the signal read from the CCD 1 by means of a correlative double sampling circuit 4, passes the signal through an analog signal processing circuit 6 performing a gain control, nonlinear processing and the like, after passing it through a low-pass filter 5 to remove clock noise, and then makes an analog-to-digital conversion in an analog-to-digital converting circuit 7 by means of a sampling pulse for analog-to-digital conversion to obtain a digital television image signal.
The correlative double sampling circuit 4 has three sample and hold circuits 4a, 4b and 4c driven by three sampling pulses whose phases are different from each other and which are generated by the CCD driving gate array 3, and derives by means of a differential amplifier 4d a difference in level between two sampled values taken by sampling the signal read from the CCD 1, namely, a sampled value (black sample, as shown in FIG. 2A) taken by sampling the signal from the CCD 1 at a black level sampling point B in a zero-signal period and a sampled value (white sample as shown in FIG. 2A) taken by sampling the signal from the CCD at a white level sampling point W in a signal period. Since the correlative double sampling circuit is set just behind the CCD 1 and processes the signal which has not passed through the analog signal processing circuit 6, the variation in phase between a sampling pulse and a signal read from the CCD 1 in this place is so slight and stable that it may not cause any problem.
The image signal obtained from the correlative double sampling circuit 4 is passed through the low-pass filter 5 and the analog signal processing circuit 6, and then is sampled by the analog-to-digital converting circuit 7. The analog-to-digital converting circuit 7 of this example is not a flash type circuit, but an ordinary type circuit having a sample and hold circuit 7a and an analog-to-digital converter 7b. The sampling pulse for analog-to-digital conversion for determining a sampling timing in the sample and hold circuit 7a of the analog-to-digital converting circuit 7 is generated by the reference oscillator 2. In this manner, the timing of reading the signal from the CCD 1 and a timing of sampling in the analog-to-digital converting circuit 7 are coincident with each other.
In the above mentioned solid state image pickup apparatus having CCD 1, when a phase of the sampling pulse for analog-to-digital conversion in the analog-to-digital converting circuit 7 is correct relative to a phase of the sampling pulse in the correlative double sampling circuit 4, a signal as shown in FIG. 2B is entered into the low-pass filter 5 and a signal as shown in FIG. 2c is read out from the low-pass filter 5 upon picking up an image of a black and white stripe pattern having a maximum spatial frequency in a manner shown in FIG. 3. The signal is sampled at an ideal level as shown in FIG. 2E if being sampled by a sampling pulse for analog-to-digital conversion having an ideal phase as shown in FIG. 2D. In this manner, an analog image signal which has been read from the CCD 1 and sampled in the correlative double sampling circuit 4 is converted into a digital image signal having a desired maximum spatial frequency. However, if the phase of the sampling pulse for analog-to-digital conversion deviates from the ideal phase as shown in FIG. 2F, sampling at an ideal level cannot be performed in the analog-to-digital converting circuit 7 and as a result the original black and white stripe pattern cannot be reproduced as shown in FIG. 2G. In order to set the sampling timing as a desired timing, a pulse phase adjuster 8 is provided for adjusting a phase of the sampling pulse for analog-to-digital conversion to be supplied from the reference oscillator 2 to the sample and hold circuit 7a of the analog-to-digital converting circuit 7. And pulse phase adjusters 9 and 10 are also provided so as to adjust phases of sampling pulses to be supplied to the correlative double sampling circuit 4. Each of the pulse phase adjusters 8 to 10 is a circuit for manually adjusting a pulse phase and is composed of a variable resistor, capacitor and buffer amplifier, but the pulse phase can be also adjusted by means of other methods than this.
In the known solid state image pickup apparatus shown in FIG. 1, the analog image signal is converted into the digital image signal by means of the ordinary analog-to-digital converting circuit 7 having the sample and hold circuit 7a and analog-to-digital converter 7b, but the conversion may be equally carried out by means of a flash type analog-to-digital converting circuit having no sample and hold circuit instead of such an analog-to-digital converting circuit. In this case, the sampling pulse for analog-to-digital conversion may be supplied to the analog-to-digital converter 7b as shown by a chain line in FIG. 1.
As described above, the pulse phase adjusters 9 and 10 are provided for adjusting a timing for sampling the signal read from the CCD 1 in the correlative double sampling circuit 4 and the phase adjuster 8 is provided for adjusting a phase of the sampling pulse for analog-to-digital conversion in the analog-to-digital converting circuit 7. In the initial setting, the pulse phases are adjusted by means of these pulse phase adjusters so as to obtain the optional phase relation. However, since there is the possibility that the phase relation between the sampling pulses will deviate from an ideal one while the solid state image pickup apparatus is used, it is necessary to readjust the phase relation. The reasons are that a time lag from a point in time of receiving a clock signal from the reference oscillator 2 to a point in time of generating a CCD driving pulse varies from about 10 to 20 ns for respective devices and changes of temperature since the CCD driving gate array 3 is of MOS structure, that a time lag from a point in time of receiving a sampling pulse to a point of time of making an actual sampling operation in the flash type analog-to-digital converting circuit 7 varies also about ten and several ns, and that a phase relation between a signal to be supplied to the analog-to-digital converting circuit 7 and a sampling pulse is affected by a time lag caused by the low-pass filter 5 and analog signal processing circuit 6 which give a time lag to a signal, since the flash type analog-to-digital converting circuit 7 is provided behind the low-pass filter 5 and analog signal processing circuit 6.
Therefore, there is the disadvantage that a desired image signal could not be obtained as a result of the optional timing of sampling a shown in FIGS. 2C and 2D is lost after the initial setting. As described above, since a phase deviation in the correlative double sampling circuit 4 is not so great, it is not always necessary to readjust the pulse phase adjusters 9 and 10, but since a time lag in the low-pass filter 5 and analog signal processing circuit 6 considerably varies with aging and temperature change, the phase adjuster 8 controlling a phase of the sampling pulse for analog-to-digital conversion to be supplied to the analog-to-digital converting circuit 7 needs to be readjusted even when it is in use.
A respective one of said deviations is small, but a total deviation is not negligible in a system for sampling the signal in a high frequency band. In a system for processing a television signal of the NTSC system of the existing color television system adopted in Japan, the sampling period is 70 ns, but there is the possibility that the sampling period will be set as 50 ns or less in the near future and then even a deviation of about 10 ns becomes unacceptable. Furthermore, in the Hi Definition Television System, where the sampling period is 14 ns, even only a very small deviation of about 1 to 2 ns is not negligible.
As described above, in the known solid state image pickup apparatus, it is necessary to readjust the sampling timing while it is in use as well as to adjust the sampling timing in the initial setting. Up to now, in case of making such adjustment, as shown in FIG. 3, a test chart 14 having a black and white stripe pattern to give the highest frequency in the horizontal scanning direction is placed in front of a solid state image pickup apparatus 13 mounted on a tripod 12. The chart is uniformly illuminated by an illuminating apparatus 15, the tripod is fixed so as to correctly direct the solid state image pickup apparatus toward the test chart in the horizontal and vertical directions, and a fine adjustment is made so that the stripe pattern cycle may become ideal to alignment of the image pickup device of the solid state image pickup apparatus. Then the pulse phase adjusters 8 and 9 shown in FIG. 1 are finely adjusted while observing an image signal obtained by the analog-to-digital conversion by means of a logic analyzer or observing it by means of an oscilloscope after converting it from a digital signal to an analog one. Such an adjusting method has a disadvantage that not only is it very troublesome and requiring of skilled but also it takes a long time to set the test chart 14 and the image pickup device of the solid state image pickup apparatus in a specified relation. Another disadvantage is that the highest-frequency image signal cannot be obtained since the sampling timing might be deviated from the ideal point if the adjustment is not exactly made. And this adjusting method also has the disadvantage that it needs the tripod 12, test chart 14 and illuminating apparatus 15 and the like and there is the possibility that readjustment cannot be performed because they cannot be set up.